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• LC3 Reference Sheet

  

Every instruction starts with 4 phase:

FSM

FSM execute microcode

Confusions:

• Clock Cycle

  You want to maximize what happens during a single clock cycle. There are 2 main obstacles that help determine what cannot happen during a single clock cycle.

  1. A register is only updated with its new value on the rising edge of the clock. If you need to use the value of the register you just set, then you must wait till the next clock cycle. An example of this would be a load instruction. If you set the value of MAR in the first clock cycle, then you must wait until the next clock cycle to read MAR. You cannot set and read from the register in the same clock cycle.

  2. Only one value can be on the bus at any given time. If you need to set 2 different registers with different values, this will take 2 clock cycles since only one value can be on the bus. An example of this would be a store instruction. You need one clock cycle to set MDR and another to set MAR.

• LD.CC

  Any time you do an instruction that changes the value of a register in the register file, you need to set the condition codes because there is a possibility that we require the sign of that value to determine branching (BR) logic. The exception to this rule is for LEA. LEA will always load into a register a binary string that represents an address. It doesn't make sense for an address to be signed, so we do not set a condition code for it. That also means you should not complete Branching logic based on LEA! It's just an address in memory. Instead, it would make more sense to load the data at that address since that could be a more meaningful value. We have made this note in the LC-3InstructionsDetail.pdf

  For the remainder of instructions that do set condition codes, since there is a possibility that they could store a meaningful number/result of math/ value (ie: not an address) into a register that means we need to set the cc's. We might not BR based on the CC each time we do one of these operations, but since that possibility does exist, we have to include setting CC in these instructions microcodes.

  EDIT: please note that when we change a value in memory (ie: perform a store) we do not set condition codes. This is because memory is not a register

Fetch

• IR <= Mem[(PC)]

  Control Instructions

  1. Clock Cycle 1:
     1. PCMUX selects PC.MUX + 1
     2. LD.PC
     3. Gate.PC - allow data to flow from PC to bus
     4. LD.MAR - Load the data to memory

  2. Clock Cycle 2:
     1. MEM.EN/R - Memory read data
     2. (MDRMUX select memory - take data from memory and send to the bus)
     3. LD.MDR - Write data into the MDR

  3. Clock Cycle 3:
     1. Gate.MDR - Write data to the main bus
     2. Load.IR - Read data to the IR

OPERATE:

Add

• Definitions

  

• DR = (SR1) + (SR2)

  Control Instruction

  One clock cycle

  1. (SR1MUX select IR[8:6])

  2. SR2MUX selects OUT

  3. ALUK select add - add SR1 and SR2 - 00

  4. GateALU - send added data to the bus

  5. LD.REG - write the data to the destination register

  6. LD.CC

• DR = (SR1) + SEXT[IR[4:0]]

  Control Instruction

  One clock cycle

  1. SR1MUX select IR[8:6] - 1

  2. SR2MUX selects SEXT[IR[4:0]] - Sign extended SR2

  3. ALUK select add - add SR1 and SR2

  4. GateALU - send added data to the bus - 1

  5. LD.CC - 1

  6. LD.REG - write the data to the destination register - 1

AND

• Definitions

  

• DR = (SR1).(SR2)

  One clock cycle

  1. (SR1MUX select IR[8:6]) - 1

  2. SR2MUX select SR2 OUT

  3. ALUK select AND - 01

  4. Gate.ALU - 1

  5. LD.CC - 1

  6. LD.REG - 1

NOT

• Definitions

  

• DR <= (SR1’)

  One clock cycle

  1. SR1MUX select IR[8:6] - 1

  2. ALUK Select NOT

  3. Gate.ALU - 10

  4. LD.CC - 1

  5. LD.REG - 1

LOADS:

LEA(LOAD EFFECTIVE ADDRESS)

• Definitions

  Puts the effective address (PC+offset) itself into a register (no memory access!)

  

• DR <= (PC) + SEXT(IR[8:0])

  One clock cycle

  1. ADDR1MUX Select PC - 0

  2. ADDR2MUX Select SEXT(PCoffset9/IR[8:0]) - 10

  3. MARMUX select ADDER - ADD also send data to MARMUX.gate instead of PC - 1

  4. Gate.MARMUX - Send data to the main bus - 1

  5. LD.REG - Take data from bus and load to destination register - 1

• Binary Encoding Example

  

LD(LOAD)

• Definitions

  Puts the contents of some memory at the effective address (PC+offset) into a register

  

  

• DR <= Mem[(PC) + SEXT(IR[8:0])]

  1. ClockCycle 1
     1. ADDR1MUX select PC - 0
     2. ADDR2MUX select SEXT(PCoffset9) - 10
     3. MARMUX select ADDER - 1
     4. Gate.MARMUX - 1
     5. LD.MAR - 1

  2. Clock Cycle 2
     1. MEM.EN - 1
     2. LD.MDR (MDRMUX selects Memory) - 1

  3. Clock Cycle 3
     1. Gate.MDR
     2. LD.REG
     3. LD.CC

  • Binary Encoding Example

LDI(LOAD INDIRECT)

• Definitions

  Goes to the effective address (PC+offset) and gets a value. Treats that value as another memory address, and gets data from there, into a register (hits memory twice)

  

  ---

  ---

  

  ---

  

• $DR <= Mem[Mem(PC)+SEXT(PCoffset9)]$

  1. Clock cycle 1
     1. ADDR1MUX Select PC - 0
     2. ADDR2MUX Select SEXT(PCoffset9) - 10
     3. MARMUX selects ADDER - 1
     4. Gate.MARMUX - 1
     5. LD.MAR - 1

  2. Clock Cycle 2
     1. MEN.EN - 1
     2. LD.MDR(MDRMUX select memory) - 1

  3. Clock Cycle
     1. Gate.MDR - 1
     2. LD.MAR - 1

  4. Clock Cycle 4
     1. MEN.EN - 1
     2. LD.MDR(MDRMUX select memory) - 1

  5. Clock Cycle 5
     1. Gate.MDR - 1
     2. LD.CC - 1
     3. LD.REG - 1

• Binary Encoding Example

  

LDR(LOAD BASE + OFFSET)

• Definitions

  Puts the contents of the effective address (base register+offset) into a register.

  

• DR < = Mem[IR[8:6] + SEXT(IR[5:0])]

  1. Clock Cycle 1
     1. ADDR1MUX selects SR1OUT - 1
     2. ADDR2MUX selects SEXT(IR[5:0]) - 01
     3. MARMUX selects ADDER - 1
     4. Gate.MARMUX - 1
     5. LD.MAR - 1

  2. Clock Cycle 2
     1. MEN.EN - 1
     2. LD.MDR(MDR.MUX select Memory) - 1

  3. Clock Cycle 3
     1. Gate.MDR - 1
     2. LD.CC - 1
     3. LD.REG - 1

STORES:

ST(STORE)

• Definitions

  Puts the contents of a register into memory at the effective address (PC+offset).

  

• Mem[(PC) + SEXT(IR[8:0])] < = SR

  1. Clock Cycle 1
     1. ADDR1MUX select PC - 0
     2. ADDR2MUX select SEXT(IR[8:0]) - 10
     3. MARMUX select ADDER - 1
     4. Gate.MARMUX - 1
     5. LD.MAR - 1

  2. Clock Cycle 2
     1. SR1 - 0
     2. ALUK selects PASS - 11
     3. Gate.ALU —> Pass to bus and send it to MDR - 1
     4. LD.MDR(MDRMUX select BUS) —> Take the source register from BUS - 1

  3. Clock Cycle 3
     1. MEM.EN - 1
     2. R.W - 1

• Binary Encoding Example

STR(STORE BASE + OFFSET)

• Definitions

  Puts the contents of a register into memory at the effective address (base register+offset)

  

• Mem[(IR[8:6]) + SEXT(offset6)] < = SR

  1. Clock Cycle 1
     1. (SR1MUX select IR(8:6))
     2. ADDR1MUX select BaseR - 1
     3. ADDR2MUX select SEXT(offset6) - 01
     4. MARMUX select ADDER - 1
     5. Gate.MARMUX - 1
     6. LD.MAR - 1

  2. Clock Cycle 2
     1. Gate.ALUK - 1
     2. ALUK select PASS - 11
     3. LD.MDR - 1

  3. Clock Cycle 3
     1. MEM.EN - 1
     2. R.W. - 1

• Binary Encoding Example

  

STI(STORE INDIRECT)

• Definitions

  Puts the contents of a register into a memory location whose address is stored in memory at the effective address (PC+offset). (Hits memory twice!)

  

• Mem[Mem[(PC) + SEXT(IR[8:0])]] < = SR

  1. Clock Cycle 1
     1. ADDR1MUX select PC - 1
     2. ADDR2MUX select SEXT(IR[8:0]) - 10
     3. MARMUX select ADDER - 1
     4. Gate.MARMUX - 1
     5. LD.MAR - 1

  2. Clock Cycle 2
     1. MEM.ER - 1
     2. LD.MDR (MDRMUX select Memory) - 1

  3. Clock Cycle 3
     1. GATE.MDR - 1
     2. LD.MAR - 1

  4. Clock Cycle 4
     1. Gate.ALUK - 1
     2. ALUK select PASS - 11
     3. LD.MDR - 1

  5. Clock Cycle 5
     1. MEM.EN - 1
     2. R.W. - 1

CONTROL:

JMP(JUMP)

• Definition

  

• PC < = (BaseR)

  1. (SR1MUX select IR[8:6])

  2. (ADDR1MUX select SR1OUT)

  3. ADDR2MUX select ZERO
     1. PCMUX select ADDER —> Add SR1 with 0(Changes nothing) and send to PC

  4. LD.PC

BR(CONDITIONAL BRANCH)

• Definitions

  nzp are conditional branch instructions, determine whether the change the instruction flow.

  During the EXECUTE phase, the processor examines the condition codes whose corresponding bits in the instruction are 1.

  If any of nzp are 0, the corresponding condition codes are not examined.

  If any of the condition codes that are examined are in state 1, then the PC is loaded with the address obtained in the EVALUATE ADDRESS phase

  • Example

    PC = x4027

    Example: 0000 010 011011001

    Assembly: BR z x0D9

    Next instruction: Instead of x4028, it would be x4028 + x0D9 = 4101

  

• PC < = (PC) + SEXT(IR[8:0]) iif (N.n + Z.z + P.p)

  1. ADDR1MUX select PC

  2. ADDR2MUX select SEXT(IR[8:0])

  3. PCMUX select ADDER

  4. LD.PC iif (N.n + Z.z + P.p)

JSR & JSRR(JUMP TO SUBROUTINE)

• Definition

  If JMP is located at x4000 and baseR is x6600, the program will execute the x4000(JMP) followed by the instruction at x6600

  

• JSR

  R7 < = (PC). PC < = (PC) + SEXT(IR[10:0])

  1. GatePC

  2. DRMUX select [111]

  3. LD.REG

  4. ADDR1MUX select PC

  5. ADDR2MUX select SEXT(IR[10:0])

  6. PCMUX select ADDER

  7. LD.PC

• JSRR

  R7 ≤ PC. PC < = (BaseR)

  • Instruction 1

    1. GatePC

    2. DRMUX select [111]

    3. LD.REG

TRAP

Trapvector: identifies the service call that the program wishes the operating system to perform

• Once the operating system is finished performing the service call, the program counter is set to the address of the instruction following the TRAP instruction.

• In this way, a program can, during its execution, request services from the operating system and continue processing after each such service is performed.

Servical Calls:

• Input a character from the keyboard (trapvector = x23)

• Output a character to the monitor (trapvector = x21).

• Halt the program (trapvector = x25)