LC3 Fundamentals

Registers

General-purpose register set

• Additional temporary storage locations that can be accessed in a single machine cycle(Since it usually takes far more than one machine cycle to obtain data from memory)

• Registers have the same property as memory locations in that they are used to store information that can be retrieved later.

• Registers must be uniquely identifiable

• identified by a 3-bit register number, R0 - R7

Data types

The only data type supported by the ISA of the LC-3: 2's complement integers.

The Instruction Set

An instruction is made up of two things, its opcode (what the instruction is asking the computer to do) and its operands(who the computer is expected to do it to)

Opcode

• The LC-3 ISA has 15 instructions, each identified by its unique opcode

• 16 distinct opcodes are possible(4 bit with 1101 reserved for future needs)

LC3 has three different types of instructions(three different types of opcode)

• Operates
  • Process information

• Data movement
  • move information between memory and the registers and between registers/memory and input/output devices.

• Control Instructions
  • change the sequence of instructions that will be executed

Operand can be found in one of three places

• Memory

• Register

• Part of the instruction - referred as literal/immediate operand

LC3 Instruction Overview

• Arithmetic Instructions
  • ADD
  • OR
  • NOT - only operation that requires only one source operand
  • XOR

• Data Movement Instructions
  • LD, ST
    • the location of the destination operand is overwritten with the source operand, destroying the prior value in the destination location in the process.
  • LDR, LDI, LEA, TR, and STI.

Addressing Modes

Specify where the operand is located

Five addressing mods

• Immediate

• Register

• PC-relative
  • LD, ST
  • Instruction specify an offset relative to PC
  • The memory address is computed by sign-extending [8:0]

• Indirect
  • LDI, STI
  • Instead of the address being the address of the operand, it contains the address of the operand to be loaded or stored.
  • LD example: PC + Offset → Get content at that address with MDR → Use the content at that address as the address → Get data at the new address

• Base + Offset
  • LDR, STR
  • the address of the operand is obtained by adding a sign-extended 6-bit offset to a base register. (Unline LD or ST where address is calculated by PC + offset, the address here is calculated by base register + offset)
  • Base+offset addressing mode also allows the address of the operand to be anywhere in the computer's memory.

Executing Instruction

Each instruction execution has three "stages", called macrostates

Each macrostate is made of one or more microstates (1 per clock cycle)

The microstates are the states in the microcontroller's state machine!

Macrostates:

Fetch

• Use PC value (address of next instruction) to read the next instruction from memory

• Load this value into the IR so that it can be decoded and executed later

• Increment the value of PC – it must always point to the next instruction to be run

Decode

• Now that the IR contains the instruction, the FSM can read the opcode.

• If the instruction is BR (branch), the FSM will also check the condition codes to ensure that the branching condition is met.

• The FSM will change to a specific state depending on the opcode. This takes a clock cycle in the LC-3, but some computers can combine DECODE with the last cycle of FETCH.

EXECUTE

• Each instruction causes the EXECUTE phase to act differently.

• The EXECUTE macrostate takes a variable number of clock cycles; some instructions like ADD are quick, while others like LDI take longer

Control Instructions

Usually, PC is incremented in the FETCH phase of each instruction, and the next instruction would be the instruction located in the next sequential memory location.

Control instructions change the sequence of the instructions that are executed

5 opcodes that enable the sequential flow to be broken:

• conditional branch

• unconditional jump

• subroutine(function) call

• TRAP

• return from interrupt

Memory(LC 3)

Read Memory

Memory is accessed by loading the memory address register (MAR) with the address of the location to be accessed.

Load Memory

control signals read the memory input(MAR), and the result of that read is delivered by the memory to the memory data register (MDR)

Store in Memory

If a store is being performed, the data to be stored is first loaded into the MDR. Then the control signals specify that WE is asserted in order to store into that memory location.